Semiconductor test time is the cost?Teradyne reveals its big killer

From design to manufacturing, to packaging and testing of chips, a lot of manpower, material resources and financial resources are spent in the process of turning sand into gold. The quality, performance, and yield of each link need to be strictly controlled. As we all know, simple chip testing cannot add functions to the chip, nor can it improve the performance of the chip. However, chip testing runs through the entire process from semiconductor R&D to mass production, and becomes an inevitable part of semiconductor manufacturing. Chip testing mainly includes wafer testing CP and finished product testing FT. Through the testing, manufacturers can find chip design and manufacturing problems in a timely manner, thereby improving chip production yield and ensuring delivery quality.

In the semiconductor test equipment market, ATE test equipment occupies two thirds of the semiconductor test equipment. Among them, Teradyne and Advantest have the strongest technical strengths, controlling 90% of the global semiconductor test equipment market share. Teradyne has strong technology accumulation and a complete semiconductor test solution to continuously ensure chip quality and reduce customer test costs. According to Huang Feihong, deputy general manager of Teradyne sales, Teradyne has launched a variety of test platforms for SoC testing, including J750, UltraFLEX, EAGLE TEST SYSTEM and other series of test equipment.

In Huang Feihong’s view, to a certain extent, the test time is equivalent to the test cost. Therefore, how to improve chip test efficiency and reduce test costs has become an urgent problem to be solved in the current semiconductor market. On the basis of UltraFLEX test equipment, Teradyne launched UltraFLEXplus, which adopts a new PACE architecture and combines with IG-XL software to add another weapon to the semiconductor test market.

Chip technology continues to drop, and test challenges become increasingly prominent

From the perspective of the evolution of the semiconductor process technology, it can be roughly divided into three eras. It can be seen that from 1990 to 2025, semiconductor technology has gradually dropped from 0.8um to 3nm or even 2nm. With the continuous evolution of semiconductor technology, chip sizes have become smaller and smaller, and the integration of on-chip transistors has become higher and higher. This means that more simulation, data transmission and interface functions are integrated on the chip. Correspondingly, chip testing technology has also evolved continuously to meet the increasingly complex functional requirements of chips.

“The evolution of advanced technology has brought about an increase in test time.” Huang Feihong pointed out that the ever-increasing chip scale continues to increase the complexity of chip design, and the test requirements for SCAN, BIST, and standardized interfaces have also increased. Take the processor chip as an example. SCAN and BIST tests are the standards for testing the maturity of the process. The smaller the process size, the longer the test time. For analog and RF chips, Trimming testing takes up more and more time.

In addition, single-station testing seriously slows down the chip testing speed and lengthens the testing time, resulting in a high proportion of the testing cost in the overall chip price. The more advanced technology goes down, the higher the requirements for parallel testing capabilities of test equipment. However, when the process drops below 10nm, the growth rate of the number of transistors has far exceeded the update speed of chip test technology, and the interface boards and test stations cannot be increased indefinitely. ATE test equipment is facing a new round of challenges.

“Another challenge (faced by ATE test equipment) is that as the process size is reduced to 10nm and below, the yield of wafers in initial mass production continues to decline.” Huang Feihong said that the die size has changed from the original die size. 200mm2 has increased to 800mm2, and the corresponding failure density has also been increasing. For a die size of 800mm2, the yield rate of wafers in the initial mass production under the 10nm process is less than 10%.

The underlying architecture is upgraded to reduce cost and increase efficiency for chip testing

Faced with more complex mobile phones, processors, radio frequency and other chips, Teradyne launched the UltraFLEXplus high-performance SoC test platform. On the basis of the UltraFLEX series test platform, the platform has a new design of the detector interface board and adopts the PACE multi-controller architecture for the first time. “From J750 to UltraFLEX to UltraFLEXplus, Teradyne has adopted a unified software platform IG-XL.” In Huang Feihong’s view, this is also Teradyne’s biggest competitive advantage. The testing procedures are fully compatible, which directly improves engineers. Development efficiency.

Different from the previous generation interface board design, UltraFLEXplus adopts the new Broadside technology, the interface board size increases, and the number of PCB layers will be significantly reduced by 20%. “If there are many PCB layers, the processing difficulty will bring greater failure rate.” On the other hand, the new interface board pins are symmetrically distributed, the layout is clearer, and the winding length is effectively reduced, which can effectively reduce the PCB Board design requirements have greatly improved signal integrity and power integrity, and parallel testing capabilities have also been improved.

“The PACE multi-controller architecture is a unique architecture of the UltraFLEXplus test platform, which can decentralize computing power and improve processing efficiency.” Huang Feihong said that the PACE architecture uses the intermediate workstation master control to decentralize all computing power to each board. Each board has an independent CPU to execute instructions and measurement calculations. In addition, UltraFLEXplus is equipped with a third-generation digital board. It adopts an open, scalable, and distributed computing architecture, which can improve test efficiency as a whole. Combined with the IG-XL software platform, it reduces engineering development time by 20% and can be more Develop a more optimized test program in less time.

Write at the end

According to Huang Feihong, the global installed capacity of the UltraFLEX test platform has reached 5,000 sets, and the installed capacity of the IG-XL software platform has exceeded 12,000. Since 2020, the global installed capacity of UltraFLEXplus has also been close to 600, and it has been installed and used in two major foundries and five OSATs. Teradyne has a wealth of experience in market verification. Within one and a half years after the launch of the new UltraFLEXplus platform, it has been widely praised by major customers and is used in the field of digital computing chips.