What This Component Is and Its Industry Significance

In modern industrial electrification, power conversion equipment must handle massive currents and high voltages while switching rapidly with minimal energy loss. The insulated-gate bipolar transistor, or IGBT, has served as the backbone of medium-to-high-power conversion systems since its commercial emergence. Within this ecosystem, dual IGBT modules occupy a prominent role, packaging two distinct switching elements into a single integrated housing to form half-bridge or dual-switch configurations. The SanRex PK200FG series represents a mature, field-proven class of industrial power modules designed to manage demanding switching regimes across manufacturing plants, transportation systems, and energy infrastructure.

Specifically, the SanRex PK200FG160 and PK200FG120 are dual IGBT modules engineered for high-power conversion. Both modules carry a nominal continuous collector current rating (IC) of 200 A, yet they diverge critically in their maximum repetitive peak collector-emitter voltage ratings (VCES). The PK200FG120 provides a breakdown threshold of 1200 V, whereas the PK200FG160 extends this dielectric ceiling to 1600 V. Understanding the distinctions between these two thresholds is central to power converter design, as voltage rating directly influences switching performance, thermal dissipation, and system reliability.

Historically, power engineers faced a challenging compromise: bipolar junction transistors (BJTs) offered low conduction losses at elevated currents but required complex, power-hungry base-drive circuits and exhibited sluggish turn-off times due to stored minority charge. Conversely, power MOSFETs permitted simple, voltage-controlled gate operation and ultra-fast switching, yet their on-state resistance scaled unfavorably at ratings above 600 V. The IGBT resolved this dilemma by merging a voltage-driven metal-oxide-semiconductor (MOS) gate structure with a bipolar output stage. By mastering this hybrid architecture, modules such as the PK200FG120 and PK200FG160 allow engineers designing equipment in power electronics to control hundreds of amperes using compact, low-power driver stages.

These two modules resolve specific challenges in industrial environments. Standard three-phase alternating current (AC) motor drives, uninterrupted power supplies (UPS), and induction heating systems require robust semiconductor switches capable of withstanding supply transients, inductive kickback, and cyclic thermal stress. By integrating dual switches along with antiparallel fast-recovery diodes into an isolated baseplate module, SanRex streamlined mechanical assembly, reduced stray busbar inductance, and simplified heatsink integration for power conversion apparatus across the globe.

Working Principle and Physical Structure

To grasp how the PK200FG160 and PK200FG120 operate under load, one must examine their internal semiconductor physics and packaging architecture. At the silicon level, an insulated-gate bipolar transistor functions as a four-layer (p-n-p-n) device controlled by an insulated gate electrode. Rather than functioning as a latching thyristor, wide-cell pitch engineering and internal emitter ballasting suppress regenerative latch-up, allowing the device to remain entirely under gate control during both turn-on and turn-off phases.

SanRex PK200FG dual IGBT module internal physical topology and silicon arrangement
Figure 1: Internal Half-Bridge Topology and Physical Terminal Architecture of Dual IGBT Modules

When an external circuit applies a positive voltage between the gate and emitter terminals exceeding the threshold voltage (VGE(th), typically between 5.0 V and 7.0 V), an electrostatic field forms across the thin silicon dioxide dielectric layer. This field repels mobile holes within the p-type body region directly beneath the gate, drawing free electrons toward the surface to create an n-type inversion channel. This channel permits electrons to stream from the n+ emitter into the wide, lightly doped n- drift layer.

The injection of electrons into the n- drift region forward-biases the p-n junction formed between the p+ collector substrate and the n- drift layer. In response, the collector substrate injects an abundance of positive charge carriers (holes) into the drift layer. This phenomenon, known as conductivity modulation, floods the high-resistance drift region with a dense plasma of both electrons and holes. Consequently, the effective bulk electrical resistance of the silicon drops by several orders of magnitude. This enables the PK200FG series to conduct 200 A with a relatively low collector-emitter saturation voltage (VCE(sat)) of approximately 3.0 V, keeping on-state conduction losses manageable.

Turn-off occurs when the gate voltage drops below the threshold, collapsing the inversion channel and cutting off the supply of electrons. However, the minority carrier holes remaining in the drift zone cannot instantly disappear; they must either recombine naturally or be swept out by the expanding depletion region. This process creates a transient “tail current” that prolongs the turn-off interval and contributes to switching energy losses (Eoff). The thicker n- drift region required by the 1600 V PK200FG160 stores a higher volume of plasma than the 1200 V PK200FG120, necessitating precise carrier lifetime management during manufacturing to ensure both devices maintain stable switching up to 20 kHz.

Mechanically, both modules utilize a Direct Bonded Copper (DBC) substrate. The DBC assembly consists of an electrically isolating ceramic tile—typically aluminum oxide (Al2O3) or aluminum nitride (AlN)—sandwiched between two copper sheets. Silicon IGBT dies and antiparallel fast-recovery diode (FRD) dies are soldered directly onto the patterned top copper layer. Thick aluminum wire bonds connect the die surfaces to the copper traces and external power terminals. The underside copper layer is soldered to a nickel-plated copper baseplate. This configuration provides over 2500 V AC galvanic isolation between the internal power circuitry and the external heatsink, while establishing a low-thermal-resistance pathway to evacuate heat generated during operation.

Key Features, Advantages, and Technology Comparison

While sharing a mechanical outline, identical continuous current ratings, and similar gate characteristics, the PK200FG160 and PK200FG120 diverge in electrical breakdown boundaries and internal semiconductor geometry. Choosing between them requires balancing dielectric withstand capability against conduction and thermal margins.

The primary technical difference lies in the blocking voltage: 1200 V for the PK200FG120 versus 1600 V for the PK200FG160. To achieve a 1600 V breakdown rating without triggering premature avalanche breakdown, the semiconductor designer must widen the n- drift layer and optimize the planar or trench edge-termination rings. A wider drift region naturally increases silicon electrical resistance. SanRex mitigates this in the PK200FG160 through proprietary vertical profiling, maintaining VCE(sat) at approximately 3.0 V under nominal conditions. Furthermore, the PK200FG160 achieves a lower junction-to-case thermal resistance (Rth(j-c)) of 0.125 °C/W compared to the 0.150 °C/W of the PK200FG120, facilitating a higher total maximum power dissipation (780 W versus 740 W).

Specification / Parameter SanRex PK200FG120 SanRex PK200FG160 Engineering Significance
Collector-Emitter Voltage (VCES) 1200 V 1600 V Peak transient blocking voltage without breakdown
Continuous Collector Current (IC) 200 A (@ TC = 25 °C) 200 A (@ TC = 25 °C) Continuous forward current handling capability
Repetitive Peak Collector Current (ICRM) 400 A 400 A Maximum permissible short-duration current spike
Collector-Emitter Saturation Voltage (VCE(sat)) Typ. 3.0 V Typ. 3.0 V Direct determinant of conduction power loss (Pcond = IC × VCE(sat))
Maximum Power Dissipation (PTOT) 740 W 780 W Maximum heat evacuation limit at specified case temperature
Thermal Resistance, Junction-to-Case (Rth(j-c)) 0.150 °C/W 0.125 °C/W Efficiency of heat flow from die to module baseplate
Maximum Switching Frequency Up to 20 kHz Up to 20 kHz Upper operating limit before switching losses dominate cooling
Isolation Voltage (VISO) 2500 V AC (1 min) 2500 V AC (1 min) Dielectric isolation between terminals and baseplate
Nominal DC Bus Operating Window 600 V to 800 V DC 900 V to 1100 V DC Recommended continuous operating link voltage with safety headroom

When evaluated alongside other industrial solutions, such as the single-switch QM300HA-H high-power module or the integrated chopper topology found in the SKD75GAL123D, the dual-pack architecture of the PK200FG series offers a balanced footprint. It provides symmetric top- and bottom-switch characteristics within a single package, substantially reducing parasitic loop inductance compared to discrete modules connected via external copper busbars.

Real-World Applications and Operating Precautions

The operational divide between the 1200 V and 1600 V ratings directly dictates where each module is deployed throughout industrial infrastructure. The primary rule governing industrial power design is maintaining adequate voltage margin above the nominal direct current (DC) link voltage to account for inductive switching spikes and utility line fluctuations.

The PK200FG120 is ideally matched to three-phase AC drives operating from standard 380 V to 480 V utility mains. Rectifying a 400 V AC line generates a nominal DC bus voltage of approximately 560 V DC, which can rise to 700 V DC or higher during motor regeneration or high-line conditions. A 1200 V rating offers a comfortable 400 V to 500 V safety buffer to absorb transient overshoots caused by stray loop inductance (Vspike = -L × di/dt) during fast turn-off events. Common applications include commercial HVAC chiller compressors, industrial conveyor drives, and standard factory automation inverters.

In contrast, the PK200FG160 is designed for higher-voltage regimes, such as equipment running on 575 V or 690 V AC utility lines, heavy industrial mining drives, traction auxiliary power units (APUs), and large-scale solar photovoltaic central inverters operating with DC links approaching 1000 V to 1100 V. In these topologies, a 1200 V device would experience fatal dielectric breakdown when confronted with minor supply surges or inductive spikes. The 1600 V rating provides the dielectric margin required to survive these severe operating conditions.

SanRex PK200FG module mounting and gate driver interface guidelines
Figure 2: Proper Gate Drive Interface and Thermal Interface Assembly Arrangement

Operating these modules reliably requires strict adherence to power engineering precautions:

  • Gate Drive Control: The gate terminal exhibits a capacitive input impedance (Cies). To ensure rapid charging and discharging of this capacitance, use a dedicated, low-impedance gate driver. Drive the gate to +15 V (±10%) during conduction to guarantee full channel inversion and minimum VCE(sat). During turn-off, apply a negative bias between -5 V and -10 V. A negative gate bias prevents spurious turn-on caused by rapid collector-emitter voltage transitions (high dv/dt) coupled through the internal gate-collector Miller capacitance (Cres).
  • Thermal Management: Because these modules can dissipate over 700 W of thermal energy during severe operating states, heatsink preparation is critical. The contact surface of the heatsink must be flat to within 50 µm over a 100 mm span, with a surface roughness (Rz) of 10 µm or less. Apply an even layer of high-performance thermal grease with a target thickness of 60 µm to 100 µm. Excessive thermal compound increases thermal resistance, while insufficient compound leaves air gaps. Fasten the mounting screws progressively using a crisscross pattern to a final torque between 2.5 N·m and 3.5 N·m to avoid cracking the internal DBC ceramic.
  • Busbar Snubbers: Despite low internal module inductance, high di/dt switching transitions (often exceeding 1000 A/µs during short circuits) across external busbars generate damaging voltage spikes. Always place low-inductance film snubber capacitors directly across the module’s positive and negative DC supply terminals.
  • Electrostatic Discharge (ESD): The MOS gate oxide layer is vulnerable to electrostatic puncture. Technicians must handle modules using grounded wrist straps, maintain antistatic workstations, and leave conductive shorting clips or foam across the gate-emitter pins until the module is permanently connected to its drive circuit.

Engineering Selection Guidelines and Field Diagnostics

Selecting between the PK200FG120 and PK200FG160 requires calculating the operating electrical boundaries, evaluating thermal dissipation under worst-case ambient conditions, and establishing adequate component derating. While high-voltage auxiliary stages may employ compact integrated modules such as the DP15H1200TO101982, main inverter half-bridges processing 200 A continuous load demands strict component selection rigor.

The primary selection formula accounts for steady-state DC bus voltage plus transient overshoot:

VCES(required) ≥ (VDC(max) + ΔVtransient) × Safety Factor

In standard practice, a safety derating factor of 1.25 to 1.35 is applied over the maximum anticipated peak transient spike. If a system runs on a 690 V AC line, the rectified peak voltage under high-line (+10%) conditions reaches approximately 1070 V DC. Factoring in turn-off inductive overshoots of 200 V brings the peak stress to 1270 V. In this case, the PK200FG120 (rated at 1200 V) is entirely unsuitable, making the 1600 V PK200FG160 the necessary engineering choice.

When troubleshooting failed equipment in the field, technicians can perform a comprehensive preliminary assessment of the module using a standard digital multimeter (DMM) equipped with diode-check and high-resistance modes. Always ensure that the system is fully de-energized, that the DC-link filter capacitors are safely discharged to below 5 V DC, and that the gate drive harness is disconnected from the module terminals before performing measurements.

Diagnostic Test Point Multimeter Configuration Normal Expected Reading Failure Indication & Underlying Root Cause
Gate-to-Emitter (G-E) Junction Resistance Mode (kΩ / MΩ) High resistance (> 10 MΩ or Out of Range) Near 0 Ω or low resistance (< 1 kΩ): Gate oxide rupture caused by overvoltage transient, electrostatic discharge (ESD), or severe driver fault.
Collector-to-Emitter (C-E) Forward Blocking Diode Check / Resistance Mode (Red on C, Black on E) Out of Range / Infinite Resistance (No forward conduction) Continuity / Low Resistance: Silicon punch-through or thermal thermal meltdown across the main drift layer due to localized thermal runaway.
Internal Freewheeling Diode (E-C) Diode Check Mode (Red on E, Black on C) 0.30 V to 0.70 V forward voltage drop Open circuit (OL) indicates bond wire detachment from severe overcurrent; 0.00 V indicates short-circuit diode silicon breakdown.
Collector/Emitter to Baseplate Insulation / High Resistance Mode (500 V Megohmmeter or DMM) > 100 MΩ (Isolated baseplate) Low resistance or continuity indicates DBC ceramic fracture, tracking breakdown, or moisture contamination compromising galvanic safety.

If field multimeter testing indicates an intact module, yet the inverter consistently reports overcurrent or desaturation faults, perform dynamic diagnostics on the bench. Use an isolated power supply and an oscilloscope to inspect the gate driver’s output waveform under load. Ensure the gate drive pulse cleanly transitions between +15 V and -8 V without ringing or excessive rise/fall times. Inspect the physical baseplate interface for signs of grease dry-out, thermal pumping voids, or mechanical bowing caused by uneven mounting torque. Systematically verifying these mechanical and electrical parameters guarantees that both the SanRex PK200FG120 and PK200FG160 deliver stable, long-term performance across demanding industrial environments.