Methods to Increase the Power of Power Electronic Devices through Series and Parallel Connections

What Power Device Scaling Is and Its Industry Significance

Modern power conversion systems continually demand higher operating voltages, higher load currents, and increased power density. In sectors such as renewable energy generation, high-power electric traction, industrial motor drives, and grid-scale energy storage, the power requirements of the system frequently exceed the maximum voltage or current capabilities of an individual semiconductor switch. When an application requires hundreds or thousands of kilowatts, design engineers must either source specialized, high-cost single components or connect multiple standard devices in series or parallel configurations.

Connecting power electronic components—such as Insulated Gate Bipolar Transistors (IGBTs), MOSFETs, and freewheeling diodes—in parallel allows the total load current to be divided among multiple devices. This multiplies the overall current rating of the converter while maintaining the voltage rating of a single device. Conversely, connecting devices in series distributes the high system DC-link voltage across multiple switches, enabling operation at voltage levels that would otherwise cause dielectric or avalanche breakdown in a single component. According to established Power Electronics Principles, modular scaling provides significant economic and logistical advantages over manufacturing monolithic semiconductor dies with extreme surface areas or ultra-thick drift layers.

The industry significance of series and parallel scaling lies in three practical areas:

• Standardization and Cost Reduction: High-volume, standardized semiconductor modules (such as standard 600V, 1200V, or 1700V packages) benefit from high manufacturing yields and lower production costs. Building high-capacity systems from parallel or series arrays of standard parts is substantially more cost-effective than using custom, low-volume components.
• Thermal Distribution: Spreading the total power dissipation across multiple discrete packages or modules expands the total effective baseplate area. This minimizes localized hot spots, reduces overall thermal resistance from junction to heatsink (R_th(j-h)), and simplifies mechanical cooling design.
• Modularity and Redundancy: Scaled arrays allow engineers to implement N+1 redundancy architectures. If one parallel branch or series sub-module degrades, the system can continue operating at derated power, improving uptime in mission-critical applications like marine propulsion and uninterrupted power supplies.

Working Principle and Physical Structure of Scaled Configurations

To understand how power devices interact when combined, one must examine the internal device physics of the switch. An Insulated-Gate Bipolar Transistor (IGBT) integrates an insulated voltage-driven MOS gate structure with a bipolar wide-base transport junction (p-n-p structure). Applying a positive gate-to-emitter voltage (V_GE) exceeding the threshold voltage (V_GE(th)) creates an inversion channel in the p-well region under the gate oxide. This channel injects electrons into the n-drift region, which forward-biases the substrate p-n junction and causes minority carrier hole injection. This conductivity modulation dramatically lowers the on-state collector-emitter saturation voltage (V_CE(sat)) during conduction.

Parallel Operation and Current Sharing Mechanisms

When multiple IGBTs are connected in parallel, the total collector current (I_total) splits into individual branch currents (I_C1, I_C2, … I_Cn). Equal current distribution depends on both static and dynamic device parameters:

• Static Current Sharing: During steady-state conduction, current division is governed by each device’s on-state saturation voltage V_CE(sat) and the forward voltage drop (V_F) of the anti-parallel freewheeling diode. Modern IGBTs designed for parallel operation feature a positive temperature coefficient of V_CE(sat) at rated current. If Device A carries more current than Device B, Device A dissipates more power, its junction temperature (T_j) rises, its V_CE(sat) increases, and current naturally shifts toward Device B. This thermal self-stabilization prevents localized thermal runaway.
• Dynamic Current Sharing: During turn-on and turn-off transitions, current sharing is dictated by gate-emitter threshold voltage (V_GE(th)), transconductance (g_fs), internal gate resistance, and parasitic loop inductances (L_σ). If Device A turns on faster due to a lower V_GE(th) or lower stray gate-circuit inductance, it temporarily carries the entire load current and experiences high dynamic turn-on losses (E_on).

Series Operation and Voltage Sharing Mechanisms

Connecting devices in series requires the total DC-link voltage (V_DC) to divide equally across each open switch during the blocking state and during high-speed switching transients.

• Static Voltage Sharing: In the off-state, each device exhibits an off-state collector-emitter leakage current (I_CES). Because I_CES varies across manufacturing tolerances and increases exponentially with junction temperature, the device with the lowest leakage current would naturally support the highest static voltage, risking overvoltage breakdown. Parallel balancing resistors (R_p) are placed across each series device to create a stiff voltage divider that dominates over internal leakage variations.
• Dynamic Voltage Sharing: During switching transitions, differences in gate driver signal delays, device turn-off delay times (t_d(off)), fall times (t_f), and reverse recovery charge (Q_rr) cause uneven voltage distribution. The switch that turns off earliest absorbs the full dV/dt transient and risks exceeding its rated breakdown voltage (V_CES). Dynamic voltage balancing is achieved through passive snubber networks (R-C-D circuits) or active gate control methods, such as active collector-gate voltage clamping with transient voltage suppressor (TVS) diodes.

Key Features, Advantages, and Technology Comparison

Selecting the optimal power scaling strategy requires balancing design complexity, system efficiency, cooling layout, and component costs. Rather than simply using the largest possible monolithic module, such as high-current units like the QM300HA-H, engineers often evaluate whether paralleling medium-power devices or implementing series topologies delivers superior system performance.

Parallel configurations are mechanically straightforward because all collector terminals share a common DC positive busbar and all emitters share the negative busbar. However, parallel designs demand layout symmetry to equalize stray inductances. On the other hand, series configurations require fully galvanically isolated gate power supplies and complex dynamic balancing circuitry, but they allow standard-voltage semiconductors to operate on medium-voltage grids without requiring bulky, low-frequency step-up transformers.

For applications with moderate power requirements, specialized half-bridge or chopper topologies such as the SKD75GAL123D provide integrated structures that streamline thermal and electrical balancing compared to discrete configurations.

Real-World Applications and Operating Precautions

Series and parallel semiconductor configurations are deployed throughout heavy industry, grid modernization, and transportation electrification.

Primary Industrial Applications

• Megawatt Central Solar Inverters: Utility-scale photovoltaic plants utilize banks of 1200V or 1700V IGBT modules in parallel to convert thousands of amperes of DC solar generation into three-phase AC grid power at 98.5%+ conversion efficiency.
• High-Power Variable Frequency Drives (VFDs): Industrial rolling mills, mine hoists, and municipal water pumps rely on paralleled IGBT bridges to deliver dynamic torque and speed control to large induction and synchronous motors.
• Medium-Voltage Traction Inverters: Electric locomotives operating on 3.0 kV DC catenary systems employ series-connected IGBTs or multi-level converters to manage high line voltages without exceeding the breakdown limits of standard silicon packages.
• Induction Heating and Arc Furnaces: Resonant high-frequency converters utilize low-inductance parallel arrays to achieve resonant tank currents reaching tens of kiloamperes. Auxiliary converters and power supplies often incorporate integrated modules such as the DP15H1200TO101982 to ensure reliable auxiliary control loops.

Crucial Engineering & Operating Precautions

Reliable operation of scaled semiconductor arrays demands strict adherence to layout, mechanical, and electrostatic rules:

1. Laminated Busbar Symmetry: In parallel configurations, parasitic loop inductance must be matched within 5% to 10% across all branches. Use flat, laminated planar busbars where the DC+ and DC- conductors overlap closely. This minimizes total loop inductance and forces identical impedance paths to each module.
2. Decoupled Gate Drives: Never connect the gate terminals of paralleled IGBTs directly together. Direct connections cause high-frequency parasitic oscillations between gates. Always insert a dedicated series gate resistor (R_G) and a small ferrite bead in series with each gate terminal.
3. Kelvin Emitter Routing: Separate the power emitter trace carrying high load current from the auxiliary gate-drive return emitter trace (Kelvin emitter). This prevents the high dI/dt in the power path from inducing a reverse voltage into the gate drive loop, which can cause spurious turn-off or excessive switching delays.
4. Baseplate Mounting and Thermal Interface Material (TIM): Ensure heatsink surface flatness is better than 50 µm over a 100 mm span, with a surface roughness (R_z) below 10 µm. Apply thermal paste uniformly at a controlled thickness between 50 µm and 100 µm. Tighten mounting screws in progressive, crisscross stages using a calibrated torque wrench to the exact manufacturer specification (typically 3.0 to 5.0 N·m for M5/M6 bolts) to prevent baseplate warping or ceramic substrate cracking.
5. Electrostatic Discharge (ESD) Protection: The high input impedance of MOS gate structures makes them vulnerable to static gate-oxide puncture. Keep gate terminals shorted with conductive foam or clips until installation, and incorporate bi-directional 16V to 18V Zener clamping diodes between gate and emitter directly at the module terminals.

Engineering Selection Guidelines and Field Diagnostics

Designing a reliable multi-device power stage requires systematic component selection, appropriate safety derating, and practical troubleshooting procedures. Industrial product portfolios such as Industrial Power Semiconductor Solutions provide modules characterized specifically for high-capacity scaling.

Current and Voltage Derating Guidelines

Devices in parallel or series configurations should never be operated at their theoretical mathematical limits. Real-world component parameter spreads require deliberate engineering derating:

• Parallel Current Derating: Apply a current derating factor of 10% to 20% to account for V_CE(sat) matching tolerances, gate delay offsets, and thermal gradients across the heatsink. The total usable converter current (I_rated) for n paralleled modules with individual rating I_C is calculated as:
  
  I_rated = n × I_C × (1 – D_parallel)
  
  where D_parallel is typically 0.15 (15% derating).
• Series Voltage Derating: For series strings, calculate the static balancing resistor values based on maximum operating temperature and worst-case leakage current mismatch (ΔI_CES). Dynamic voltage safety margins should ensure that maximum transient peak voltages remain within 80% of rated V_CES during inductive load turn-off.
• Safe Operating Area (SOA) Verification: Ensure that the combined transient trajectories of all devices remain inside both the Forward Biased Safe Operating Area (FBSOA) and Reverse Biased Safe Operating Area (RBSOA) under short-circuit and maximum fault-clearance conditions.

Field Diagnostic and Troubleshooting Matrix

When a power converter fault occurs, field engineers and technicians can rapidly assess the electrical integrity of individual devices in parallel or series assemblies using a standard digital multimeter (DMM) set to diode-test mode and high-resistance mode. Always ensure that the DC-link capacitors are completely discharged and the gate drive boards are isolated before performing measurements.

By implementing disciplined symmetrical busbar routing, dedicated gate control impedances, robust dynamic clamping networks, and appropriate engineering derating, designers can reliably scale standard semiconductor devices in series and parallel topologies to meet the demanding requirements of megawatt-class industrial power conversion.