Pathfinder of cutting-edge technology, what is Intel’s confidence to return to its peak in 2025?

At the 2021 IEEE International Electronic Devices Conference (IEDM), Intel demonstrated a number of technological breakthroughs and fully explained its future technology development direction. On December 14, Dr. Donghui Lu, vice president of Intel and co-general manager of the Strategic Planning Department of Manufacturing, Supply Chain and Operation Group, gave a comprehensive interpretation of these advanced technologies and their application directions.

For a long time, Moore’s Law has continued to lead the development of the semiconductor industry, and as the process gradually drops until the physical limit is reached, new architectures, new materials, and new packaging have gradually become new directions for continuation of Moore’s Law. According to Dr. Donghui Lu, the Intel component research team is a pathfinder for advanced technologies from Intel and the industry. These cutting-edge technologies are also weapons that guide Intel to continue Moore’s Law. Intel is confident that it will regain its leadership in process technology in 2025.

Continue to innovate and inject vitality into the continuation of Moore’s Law

According to information disclosed by Intel, in order to promote the continuation of Moore’s Law, Intel continues to innovate and make breakthroughs. On IEDM 2021, the Intel component research team released innovations in three key areas, including transistor core scaling technology, 300mm silicon wafer integrated gallium nitride-based power devices, silicon-based CMOS, and silicon-based semiconductor quantum computing.

Take the CPU as an example. The number and density of transistors are critical to CPU performance. In this regard, Intel has proposed four 2.5D/3D packaging technology development routes. EMIB technology adopts 2.5D embedded bridging scheme, applied in the packaging process of Sapphire Rapids processor. Foveros and Foveros Omni technologies make die-to-die interconnection and modular design more flexible through high-performance 3D stacking technology. Foveros Direct technology realizes copper-to-copper bonding and low-resistance interconnection, reduces the bump pitch to less than 10 microns, and greatly improves the interconnection density of 3D stacking. In hybrid bonding (hybrid bonding) technology, chemical mechanical polishing and deposition, dielectric layer planarity and warpage all affect the effect of chip bonding. With the application of cutting-edge technology, Intel has increased the package interconnection density to 10 times above.

On the other hand, Intel is gradually leading Moore’s Law into the era of Emmy. The Intel 20A node will switch to GAAFET (Intel calls it RibbonFET), which will increase logic scaling by 30% to 50% by stacking multiple CMOS transistors. For future miniaturization technology, Intel has overcome the limitations of traditional silicon channels and used 2D materials to shorten the channel length, thereby increasing transistor integration.

In terms of power and memory, Intel integrated gallium nitride-based (GaN-based) power devices and silicon-based CMOS on a 300mm wafer for the first time, while using ferroelectric memory (FeRAM) to provide 2ns low-latency reading and writing capabilities and more Large memory resources. In addition, Intel also said that in the future, new technologies such as quantum computing will gradually replace traditional MOSFET transistors. Intel has made progress in normal temperature magnetoelectric spin orbit (MESO) logic devices, spintronic materials research, and 300mm qubit manufacturing process flow.

Build integrated capabilities of design, manufacturing, and packaging

According to Dr. Donghui Lu, the chip manufacturing process node continues to iterate with Moore’s Law, its component density continues to increase, the area occupied by existing functional modules is gradually reduced, the number and types of IP increase, and the overall chip cost continues to decrease. However, the current market application requirements have gradually increased energy efficiency and computing power requirements, and chip packaging has gradually developed in the direction of heterogeneous integration. This also means that wafer manufacturing and packaging technology is becoming more and more important.

In terms of chip manufacturing and advanced technology, Intel’s iterative upgrades during the 14nm period + + +, and the lack of mass production of the 10nm process at that time, and AMD has advanced to 7nm or even 5nm process. Therefore, Intel was once dubbed “toothpaste squeeze” by the consumer market. However, from the perspective of transistor density, Intel 10nm can be equivalent to TSMC 7nm. Generally speaking, the industry regards the gate length of the transistor as a method to guide the naming of the fab, and the current naming rules of the fab process no longer have practical significance. Compared with TSMC and Samsung, Intel’s naming method is too conservative. Intel seems to have finally realized this. In July of this year, Intel announced a new node naming method.

The new node naming method changes the name of 10nm Enhanced SuperFin to Intel 7. Compared with 10nm SuperFin, the performance per watt is increased by about 10% to 15%. The previous Intel 7nm was renamed Intel 4, which is Intel’s first FinFET node that fully adopts EUV lithography technology. Mass production is expected in the second half of 2022. Intel 3 replaced the original 7nm+ and continued the FinFET transistor architecture. Mass production is planned for the second half of 2023. At the 3nm process node, Samsung has switched to GAAFET, while Intel and TSMC still insist on continuing to evolve on FinFET. At the Intel 20A (A means “angstrom”) node, Intel switched to the GAAFET transistor architecture and introduced a new PowerVia technology, which is expected to be launched in 2024.

In fact, since Intel’s new CEO Pat Kissinger took office, a number of major strategic decisions have been announced. He emphasized that in the IDM 2.0 era, Intel will be committed to building core technology capabilities that integrate design, manufacturing, and packaging. In terms of packaging, Intel Foundry Services (IFS) combines leading process and packaging technology to continuously deliver a world-class IP portfolio to customers.

Write at the end

The birth of a chip begins with chip design, followed by mask production, manufacturing, wafer sorting, packaging and testing, and finally finished product shipments. During this period, it takes a lot of money and time costs. Dr. Donghui Lu said that with sufficient funds and time, any company can achieve technological iteration, but Moore’s Law is still an economic law in the final analysis. What companies must do is to reduce costs and improve market competitiveness. Intel’s technical team continues to lead the advancement of cutting-edge technology, guide the semiconductor field, and continue to provide the driving force for Intel’s goal of returning to its peak in 2025.

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