7MBR35SB-120 Fuji Electric 1200V 35A PIM Power Module

Content last revised on October 1, 2026

7MBR35SB-120 Circuit Protection and Reliability: Calibrating Desaturation Detection

Measure the gate to emitter and collector to emitter behavior with the DC link isolated, then compare the switching waveform with a known good phase before changing the protection threshold. The 7MBR35SB-120 is specified as a Fuji Electric PIM power module with a 1200.0 V rated voltage and 35.0 A rated current; these are official device ratings, not a complete short circuit operating area for every inverter topology.

Desaturation protection belongs to the external gate driver and control system. Its threshold, blanking interval, fault latch behavior, and soft turn off profile must be selected from the actual driver architecture and switching test results. A protection circuit that reacts too slowly may allow excessive collector emitter stress, while an overly sensitive circuit may interpret normal switching recovery or measurement noise as a fault. The correct calibration method is to observe the collector emitter voltage, gate emitter voltage, collector current, and driver fault signal together during controlled tests.

For regenerative braking systems, the braking resistor and chopper path deserve the same attention as the motor inverter bridge. During deceleration, the DC link can rise while the energy absorption path is being activated. The resistor rating, chopper switching behavior, DC link capacitance, and braking duty cycle are system determined. Designers should verify that the measured DC link and collector emitter voltage peaks remain within their applicable limits under the highest expected regenerative event, including the contribution of wiring inductance and switching overshoot.

A two stage soft turn off sequence is an engineering recommendation when the driver and power stage require controlled fault interruption. The first stage limits the current transition, while the second stage completes turn off after the driver has established a stable fault state. This approach must be validated against the actual gate charge, driver output impedance, current level, and stray inductance. It should not be treated as an official internal function of this specific module unless confirmed in the applicable Fuji Electric documentation.

During field troubleshooting, inspect the gate resistor, gate return path, isolation barrier, fault latch, and current feedback path as one circuit. A desaturation fault may indicate excessive switching overshoot, inadequate gate drive, a sensing layout problem, load commutation stress, or a genuine abnormal current event. Capture the signal at the driver terminals with a suitable probing method and compare the timing against the complementary switch. Avoid diagnosing the module from a single low bandwidth voltage reading.

The Fuji Electric reference for PIM power module architecture provides useful context for evaluating how integrated power modules are normally applied: Fuji Electric PIM power modules. This industry reference does not replace the specific electrical limits and application conditions for the 7MBR35SB-120.

Transient Dynamics and Electrical Design: High Frequency Common Mode Bearing Current

Probe the motor terminals, DC link, and protective earth during the first switching test, then compare the waveform at the inverter output with the waveform at the motor end of the cable. Long motor leads can interact with cable impedance, motor input capacitance, and switching edge rate, creating reflected voltage and common mode current. The resulting stress is determined by the complete drive installation rather than by the module rating alone.

Common mode bearing current is commonly investigated by checking the high frequency return path from the inverter bridge through the motor frame, cable shield, machine structure, and protective earth. A discontinuous shield termination or an unintended capacitive return path can shift current through motor bearings. Engineers evaluating the 7MBR35SB-120 in a precision stepper or BLDC servo motion actuator should examine the cable construction, shield bonding, motor frame connection, encoder interface, and controller reference together.

Output filters and common mode chokes should be selected from measured dv/dt, cable length, motor insulation capability, leakage current, and control loop requirements. There is no universal filter value that can be assigned to this module. Excessive filtering can alter current regulation and create resonance, while insufficient filtering may leave the motor and encoder exposed to undesirable common mode transients. The system engineer should validate the filter response with voltage and current measurements at both ends of the motor cable.

Thermal integration also affects transient reliability. The specified package is a Fuji Power Module, so the mounting surface, thermal interface material, heatsink flatness, and clamping method must be controlled as an assembly. A thin, continuous thermal interface layer is a design consideration, but its final thickness and material should follow the selected interface supplier and the measured surface condition. Voids, contamination, or uneven pressure can increase thermal impedance and produce local temperature differences between switching elements.

When the module is installed on a heatsink, use a controlled cross pattern for fastener tightening and verify the mechanical procedure against the module and heatsink manufacturer instructions. Do not infer a device specific mounting torque from the electrical ratings. Practical reminder: disconnect the DC link and verify discharge before connecting or removing motor and gate driver cables.

For a regenerative braking chopper, measure the resistor current and DC link voltage at the same time as the module temperature. A resistor that absorbs energy correctly at low repetition may still exceed its thermal capability during repeated servo deceleration. The energy path, pulse repetition, braking transistor switching frequency, and cooling arrangement are system conditions that require validation on the finished drive.

The rectifier stage should also be assessed for commutation behavior and DC link ripple. Engineers may evaluate the 7MBP10PE120 as a separate power module for a suitable design, subject to its own specifications and the complete system design. It should not be treated as an automatic companion or replacement for the 7MBR35SB-120.

Assembly Integrity and Layout Architecture: Implementing PCB Gate Loop Symmetry

Measure the gate emitter waveform directly at the module terminals and compare it with the driver output before investigating control software. A difference between the driver signal and the device terminal signal can indicate gate loop inductance, common emitter coupling, probe reference error, or an unsuitable return path. The measurement must include the actual power module connection, not only a test point on the controller board.

The gate drive loop should be compact and arranged so that the outgoing gate path and returning emitter path have closely coupled current flow. The main high current emitter connection should remain separate from the gate driver return. If the auxiliary emitter or sense return shares impedance with the power emitter path, the voltage generated by the load current transition can appear as false feedback at the driver. This can lead to unwanted gate modulation, oscillation, or inconsistent switching between phases.

For a three phase motion actuator, apply the same geometric discipline to each phase. Keep the gate resistor and any turn on or turn off shaping components close to the relevant module terminals. Route complementary switch signals with clear separation from high dv/dt collector nodes, and maintain the clearance and creepage required by the working voltage, insulation system, pollution environment, and applicable safety design rules. These are design considerations rather than published physical dimensions for this specific module.

Gate driver dead time must be established from the measured turn off and turn on behavior of the complete power stage. Device temperature, load current, driver propagation delay, gate resistance, and isolation delay all influence the required interval. Excessive dead time can increase diode conduction and distortion, while insufficient dead time can create cross conduction. Engineers should verify the actual switch node and both gate emitter signals over the full operating range.

Optocouplers and digital isolators require separate evaluation for common mode transient immunity. The selected isolation component, isolated power supply, PCB spacing, and gate driver input filter must tolerate the switching environment generated by the inverter. A high CMTI specification alone does not prove correct operation when the isolation return path and local decoupling are poorly arranged. Check the isolated driver supply, input state, fault feedback, and gate waveform during rapid DC link transitions.

For bench diagnosis, first confirm continuity of the gate resistor and emitter return, then inspect solder joints, terminal pressure, busbar position, and board contamination. Compare phase waveforms under the same current direction and switching command. A mismatch between phases may arise from assembly tolerance, driver propagation differences, unequal parasitic inductance, or a device condition. The measurement should distinguish these possibilities before a module replacement decision is made.

When evaluating a neutral alternative for a repair, compare the electrical ratings, package interface, terminal arrangement, gate characteristics, thermal path, protection behavior, and control board compatibility. The 7MBR35VP120-50 can be reviewed as a separate candidate in an engineering comparison, but substitution requires verification of the complete mechanical and electrical interface.

7MBR35SB-120 Operational Boundaries: Evaluating High dv/dt Cross Conduction Limits

Observe both complementary gate emitter signals and the switch node at the same time when investigating shoot through or unexplained DC link current. A high dv/dt transition can couple through parasitic capacitance into the opposite gate circuit, but the observed event may also involve driver timing, isolated supply movement, emitter inductance, or an incorrect measurement reference.

An active Miller clamp can be considered when the selected gate driver supports it and the measured switching environment indicates susceptibility to unintended gate voltage movement. The clamp must be positioned and connected according to the driver design, with a low impedance path to the appropriate emitter reference. Its effectiveness depends on the driver current capability, gate loop inductance, collector voltage transition, and the voltage threshold at which the clamp engages.

Negative gate bias is another possible design option, but a value must not be assigned without confirming the module gate emitter limits and the gate driver architecture. The applicable Fuji Electric documentation, driver isolation supply, gate resistor network, and switching test results determine whether positive only drive or bipolar drive is suitable. Applying an unverified negative voltage can create a separate gate stress condition.

Cross conduction testing should begin at controlled current and voltage conditions, with the DC link rise, gate timing, switch node ringing, and driver fault response recorded. Increase the operating condition only after the waveform remains stable and the measured voltage margins have been checked against the system DC link. A current spike can result from reverse recovery, output capacitance charging, control overlap, or measurement loop pickup, so the probe arrangement should be verified before assigning a cause.

In a servo actuator, rapid command changes and regenerative transitions can expose weaknesses that are not visible during steady speed operation. Test acceleration, deceleration, reversal, and braking resistor activation separately. The controller dead time, current loop bandwidth, motor cable arrangement, DC link capacitance, and gate drive behavior should be reviewed as a coordinated system. The 1200.0 V official voltage rating and 35.0 A official current rating do not by themselves define allowable switching overshoot, short circuit duration, or thermal cycling performance.

Use the Precision Gate Drive Design reference when reviewing gate loop placement, isolation behavior, Miller control, and switching waveform verification. Final acceptance should be based on measured voltage, current, temperature, and protection response in the intended equipment.