CM35MXA-24S Mitsubishi Electric 1200V 35A IGBT Module

Content last revised on October 12, 2026

Benchtop Waveform Tuning: Mitigating Commutation Turn-Off Voltage Spikes on CM35MXA-24S

• Isolate the DC link, verify discharge, and identify the main and gate terminals before connecting a meter to the CM35MXA-24S.
• Record unpowered main-terminal diode-check readings in both polarities, with the gate held in its specified off-state condition.
• Inspect the mounting surface, terminal alignment, and thermal interface for conditions that could distort the module or impair heat transfer.
• Check gate-driver return routing and probe connections before capturing switching waveforms.

The Mitsubishi Electric CM35MXA-24S is an IGBT module with a 1200 V voltage rating and 35 A current rating. These electrical boundaries provide the starting point for component identification; operating capability also depends on the manufacturer’s rating conditions, cooling arrangement, and switching duty.

For potential integration into high-dynamics multi-axis CNC or robotics servo drives, designers should compare the original power-stage schematic, mechanical interface, and gate-driver requirements before accepting a replacement. The separately listed CM400C1Y-24S is a comparison reference, not an established direct replacement for CM35MXA-24S; model-family resemblance does not establish terminal, switching, or thermal compatibility.

Capture collector-emitter voltage, collector current, and gate-emitter voltage together so that an overshoot can be located within the actual commutation sequence. As a Design Consideration, distinguish voltage rise during IGBT turn-off from ringing associated with freewheeling-diode reverse recovery during complementary-device turn-on. These events can share the same power loop but respond differently to gate-resistance changes.

Where the circuit uses an antiparallel freewheeling diode, examine its reverse-current peak and the abruptness of recovery under representative current and temperature conditions. A sharp recovery transition can excite the loop’s parasitic inductance and capacitance. Compare captures using consistent probe placement and adequate instrument bandwidth; an apparent spike that changes substantially with the probe loop deserves measurement scrutiny before hardware modification.

Engineering Recommendation: evaluate turn-on gate damping against diode recovery, switching loss, and gate-waveform stability together. Increasing damping can moderate commutation, but the resulting loss and temperature changes must remain acceptable for the intended duty. An RC snubber should likewise be evaluated against measured ringing and dissipation rather than selected from the module’s voltage rating alone. Neither adjustment establishes equipment-level EMC compliance.

A practical layout recommendation is to keep the outgoing and returning commutation paths closely coupled and geometrically balanced, then verify the resulting voltage margin with a controlled double-pulse test. Short gate connections and a deliberate driver-return path help prevent power-current transients from appearing as unintended gate excitation. Preserve the required electrical separation while reducing loop area; clearance and creepage depend on the complete insulation design and installation conditions.

For manufacturer application resources, use Mitsubishi Electric Power Semiconductors & High-Power Modules. Gate-drive decisions should follow the relevant device documentation rather than assumptions carried over from a different semiconductor generation.

Assembly Integrity & Layout Architecture: Checking Cold-State Main-Terminal Impedance for CM35MXA-24S

Disconnect parallel circuit paths before interpreting diode-check readings across the main terminals. As a Design Consideration, capacitors, snubbers, driver components, and other semiconductor branches can alter a handheld meter’s response. Record polarity, terminal pair, temperature, and whether the measurement was made in circuit so that comparisons remain meaningful.

Where an antiparallel diode is identified in the terminal diagram, compare its forward and reverse responses with the documented circuit arrangement and a known-good reference measured under equivalent conditions. A persistent low-impedance reading warrants further isolation and investigation; a particular displayed forward voltage is not, by itself, proof of serviceability. A multimeter also cannot establish blocking performance at operating voltage.

Gate checks require similar restraint. Low-voltage resistance screening can reveal an obvious conductive path, but quantitative gate-leakage assessment requires a controlled test voltage and current measurement within the specified gate limits. Protect the gate against static charge and avoid allowing test connections to leave it floating during main-terminal checks. IGBT gate control is not a thyristor trigger-current test, so IGT/VGT pulse-trigger criteria are not applicable substitutes.

Disconnect gate-driver and power connections only after the DC link has been isolated and its discharged state verified.

For a high-side driver that uses a bootstrap supply, Engineering Recommendation: determine the charge requirement from gate charge, driver quiescent consumption during the longest uninterrupted high-side interval, and leakage. Select the capacitor and recharge path around the permitted supply droop, driver undervoltage threshold, operating sequence, and effective capacitance under bias. This is a driver-system calculation, not a fixed CM35MXA-24S capacitor requirement.

The CM400HG-66X can be reviewed separately when mapping other power-semiconductor positions in a system. Its presence in a component catalogue does not establish a rectifier role, shared gate supply, or compatibility with this module. Confirm those relationships from the equipment schematic.

Preventing Spurious Faults: SCSOA Overcurrent Protection Guidelines for CM35MXA-24S

Trace the protection signal from the current or desaturation detector through the driver to the gate waveform, including blanking, propagation, and shutdown behavior. Engineering Recommendation: assess the complete response against the device’s documented short-circuit safe operating area and its stated test conditions. A generic microsecond response target is not a verified CM35MXA-24S withstand rating.

Distinguish a device turning on into an existing short circuit from a short circuit developing during conduction. These conditions can produce different current and desaturation trajectories. Review detector behavior during normal switching first: diode recovery, displacement current, and sensing-loop coupling can resemble a fault transient. Blanking should reject legitimate switching disturbances without concealing an actual overcurrent event.

A staged soft turn-off is a Design Consideration for limiting inductive voltage rise during fault interruption. Its usefulness depends on the driver’s controlled discharge behavior and the energy remaining in the circuit. Evaluate the trade-off between reducing current fall rate and extending semiconductor dissipation, using a suitably protected test arrangement. Protection reset and restart inhibition also need verification so that the controller does not immediately reapply drive into an unresolved fault.

Miller-induced gate excursions deserve separate attention when the opposite switch commutates. Review driver sink capability, gate-return impedance, and any clamping function against measured gate-emitter voltage. Select the suppression approach from the documented gate limits and observed behavior, rather than imposing an arbitrary negative bias.

The distributor article Unlocking Efficiency in Industrial Drives provides broader switching-technology context; it does not establish that CM35MXA-24S uses the technology discussed. For insulation terminology, Dielectric Strength and High-Voltage Breakdown Testing explains the underlying concept, not this module’s isolation rating. Any insulation test should follow the applicable manufacturer procedure, with connected electronics isolated as required to prevent unintended test stress.