Content last revised on November 2, 2026
Field Diagnostics & Commissioning: Transient Thermal Impedance in CM100TX-24S Topologies
Disconnect the gate-driver connections and verify the terminal polarities against the circuit diagram before taking cold-state readings on a CM100TX-24S. With the DC link discharged and the module isolated from parallel circuit paths, record diode-mode readings in both directions across each documented power-terminal pair. Compare equivalent paths under the same instrument settings and temperature; a single forward-voltage reading does not establish switching performance.
The Mitsubishi Electric CM100TX-24S is an IGBT module rated at 1200 V and 100 A under its specified conditions. For incoming inspection, establish a repeatable baseline covering terminal identification, gate-path leakage checks, power-path measurements, and mounting-surface condition before proceeding to powered evaluation.
Bench Tip: Use ESD protection and keep the gate referenced to its emitter during cold-state comparison measurements to prevent charge-induced misleading readings.
Capture the overload pulse duration, repetition pattern, and case-temperature measurement location before estimating junction heating. As a Design Consideration, a short pulse and a sustained overload require different thermal treatment: steady-state junction-to-case resistance describes the settled heat-flow relationship, whereas transient thermal impedance describes how that relationship develops with time.
The official specification for IGBT junction-to-case thermal resistance is 0.20 °C/W per IGBT. The specified power dissipation is 625 W per IGBT at a case temperature of 25 °C, and the operating junction-temperature range is −40 to +150 °C. The dissipation figure is conditional on case temperature; it is not an allowance that can be carried unchanged into a warm enclosure.
For an Engineering Calculation, the junction temperature during an isolated rectangular loss pulse can be estimated as pulse power multiplied by the junction-to-case transient thermal impedance at that pulse duration, added to the initial case temperature, assuming an initially equilibrated device and approximately constant case temperature. For repeated or irregular pulses, a manufacturer-supported multi-RC thermal model allows the temperature contribution of preceding pulses to remain in the calculation. Its resistance and time-constant values must represent this module rather than being inferred from the steady-state resistance alone.
As an Engineering Recommendation, correlate the calculated temperature trace with measured case temperature and the actual loss waveform. Inspect heatsink flatness, mounting contact, and thermal-interface coverage when measured case heating differs between comparable operating points. A case sensor cannot directly resolve the junction-temperature peak during a brief overload.
Mechanical pressure is part of the thermal path, but press-pack disc-spring calibration and double-sided cooling must not be assumed for this module. Use its package drawing and mounting instructions to establish the fastening arrangement. The Mitsubishi Electric power semiconductor resources provide the appropriate manufacturer context for interpreting module ratings and application guidance.
Assembly Integrity & Layout Architecture: Implementing Desaturation Detection for CM100TX-24S
Trace the desaturation sensing connection and its return path before energizing the gate driver. As a Design Consideration, switching-node coupling into the sense circuit can produce nuisance trips, while excessive filtering can delay detection of a genuine fault. Keep the sensing path separated from high-current commutation conductors and evaluate its waveform against the driver’s local reference.
A type-I short circuit involves turn-on into an existing fault; a type-II event develops while the device is already conducting. These conditions place different demands on detection and turn-off. Neither a fixed microsecond clearing target nor a short-circuit withstand duration should be assigned to the CM100TX-24S without its applicable safe-operating-area conditions. The protection budget includes sensing delay, blanking, driver propagation, and current extinction.
Two-stage soft turn-off is a system-level option for reducing abrupt current interruption and associated inductive overshoot. As an Engineering Recommendation, evaluate the complete gate and collector waveforms during controlled protection testing: slowing the transition reduces current slew but can increase fault energy. The final behavior depends on the driver, gate network, bus arrangement, and operating temperature.
The following comparison separates the supplied CM100TX-24S specifications from the information needed before evaluating another repair candidate.
| Selection checkpoint | CM100TX-24S | UM100CDY-10 evaluation requirement |
|---|---|---|
| Collector-emitter voltage | 1200 V — Official Specification | Consult Datasheet: independently establish voltage and current ratings, circuit configuration, terminal mapping, gate requirements, thermal characteristics, insulation test conditions, and mounting compatibility before considering substitution. |
| Collector current | 100 A under the specified datasheet conditions — Official Specification | |
| Gate-emitter voltage limit | ±20 V — Official Specification | |
| Power dissipation per IGBT | 625 W at case temperature 25 °C — Official Specification | |
| IGBT junction-to-case thermal resistance | 0.20 °C/W per IGBT — Official Specification | |
| Isolation test voltage | 2500 Vrms AC for 1 minute — Official Specification | |
| Operating junction temperature | −40 to +150 °C — Official Specification |
A repair worksheet can include UM100CDY-10 as a separate comparison item, not an established interchangeable replacement. The ±20 V gate-emitter rating is a limiting value, not a recommended drive setting. Likewise, the isolation test rating does not independently establish continuous working voltage, permissible assembly clearance, or suitability for repeated withstand testing.
For complementary switching paths, assess dead time together with propagation mismatch, turn-off behavior, and hardware interlocking. The principle of dead-time insertion explains non-overlap, but the required interval remains system-determined. When reviewing associated converter stages, the CM900DUC-24S comparison offers separate device context; its driver or protection settings should not be transferred to this module.
CM100TX-24S Thermal-Electrical Optimization: Short-Circuit Energy Let-Through Matching Practical Tuning
Compare the protective fuse’s total-clearing characteristics with the actual DC-link fault circuit before treating it as module protection. As a Design Consideration, fuse I²t describes current-squared exposure during interruption; it is not interchangeable with the semiconductor’s internal fault-energy limit. Prospective current, capacitor discharge, circuit inductance, and DC interruption capability all affect coordination.
Fast electronic protection and upstream fault isolation serve different purposes. Desaturation protection acts through the gate driver, while the fuse addresses sustained fault current and circuit isolation. A suitable fuse cannot, by itself, guarantee that a semiconductor package remains intact during every short circuit. Qualification should examine the complete interruption sequence under the equipment’s defined fault conditions.
An MOV network also requires coordination rather than selection by module voltage alone. As an Engineering Recommendation, assess clamping behavior at the expected surge current, repetitive energy exposure, and interaction with the DC-link voltage. An MOV across a remote supply path does not automatically control a local collector-voltage spike. Local commutation geometry and snubber behavior should be assessed separately; Mastering Power System Dynamics provides related discussion of stray inductance and snubber design.
When evaluating the CM100TX-24S for commercial string inverters or micro-grid energy-storage converters, match the circuit configuration, terminal interfaces, cooling arrangement, and protection behavior to the equipment design. During controlled commissioning, capture collector voltage, gate voltage, and current on a common time reference. Use those traces to determine whether an abnormal peak originates during commutation, protection intervention, or supply-side disturbance before changing the suppression network.